1. Field of the Invention
The present invention relates to a vertical MOS transistor having a trench structure.
2. Description of the Related Art
As a discrete power transistor, in recent years, instead of a bipolar transistor, a MOS transistor in which driving power has been improved and the cost has been reduced, comes to be used. Since this power MOS transistor has such a structure that current is made to flow in the direction vertical to a substrate, this is called a vertical MOS transistor, and is frequently used for a case where a large current of, for example, an ampere class is controlled, as an external driver of an IC in a case where a low power consumption and low ON resistance are needed, or the like. In particular, a vertical trench DMOS transistor using a trench structure as shown in FIG. 3 has a merit that a cell pitch is made minute without increasing a parasitic resistance as compared with a conventional planar type vertical DMOS transistor. FIG. 2 is a planar type vertical DMOS comprising an Nxe2x88x92 epitaxial layer 2 on an N+ substrate 1,gate oxide on the surface of the Nxe2x88x92 epitaxial layer 2 and a gate electrode 5 on the Nxe2x88x92 layer 2, and has a double diffused drain structure.
Then the vertical trench DMOS has been the mainstream as a structure capable of obtaining a small size, low cost, and low ON resistance.
The structure of FIG. 3 having the trench structure is an example of an N-channel MOS. This structure is formed in such a manner that a semiconductor substrate in which a low concentration N-type layer 2 is epitaxially grown on a high concentration N-type substrate 1 which becomes a drain region, is prepared, a P-type diffusion region 20 called a body region is formed from the surface of this semiconductor substrate by impurity implantation and high temperature heat treatment at 1000xc2x0 C. or more, and a high concentration N-type impurity region 21 which becomes a source region and a high concentration P-type impurity region 22 for fixing the potential of the body region by ohmic contact are formed from the surface.
For the purpose of making the high concentration N-type impurity region 21 which becomes the source region have the same potential as the high concentration P-type impurity region 22 in FIG. 3, a contact layout is adopted, and although not shown, contact of both the regions is made by one contact hole. Then, single crystal silicon is etched through the P-type diffusion region 20 and the high concentration N-type source region 21 to form a silicon trench 23, and a gate oxide film 4 and a gate electrode 5 made of polycrystalline silicon are embedded in this silicon trench 23.
By the structure as described above, this structure can be made to function as a vertical MOS transistor in which a current flowing from the rear side high concentration N-type drain region 1 and the low concentration N-type drain region 2 to the surface side high concentration N-type source region 21 is controlled by the gate electrode 5 embedded in the trench 23 through the gate oxide film 4 at the side wall of the trench. A P-channel MOS can be formed by inverting the conductivity type of the diffusion of FIG. 3.
The structure and manufacturing method of such a vertical MOS transistor are disclosed in, for example, U.S. Pat. No. 4,767,722.
However, in the structure and manufacturing method of such a vertical MOS transistor, there exist problems as follows:
First, the relation between the depth of the trench 23 and the depth of the P-type diffusion region 20 which becomes the body region has a very important influence on the characteristics of the vertical MOS transistor. For example, if the depth of the P-type diffusion region 20 which becomes the body region is deep as compared with the depth of the trench 23, even if the body region adjacent to the gate oxide film 4 is inverted by the gate electrode 4, the P-type diffusion region 20 which is not inverted and becomes the P-type body region exists between the inverted channel region and the N-type low concentration drain region 2, so that a current can not be made to flow between the drain and the source. In the case where the depth of the trench 23 is excessively deeper than the P-type diffusion region 20 which becomes the body region, although this structure can be made to operate as a transistor, an area where the N-type low concentration drain region 2 overlaps with the gate electrode 5 through the gate oxide film 4 becomes large, and the gate-drain capacitance becomes large by this. This capacitance impedes a high frequency operation. Here, although the P-type diffusion region 20 which becomes the body region is formed by diffusing an implanted impurity through the high temperature heat treatment, since fluctuation in a high temperature heat treatment condition is low, fluctuation in the diffusion length is low.
On the other hand, in silicon etching for forming the trench 23, since there is no indicator used for stopping the etching to a desired etching depth, the etching depth is controlled through a time. However, in an anisotropic dry etching apparatus used here, since an etching rate is fluctuated by changes in apparatus temperature, gas flow rate and distribution, and the like, the total amount of etching, that is, the trench depth is apt to fluctuate. Then, normally, in order to make it possible that the transistor operation can be made even if the depth of the trench 23 becomes shallow because of fluctuation, the amount of etching is set to a valve rather larger than a target value. Thus, the foregoing gate-drain capacitance is redundantly added, and there occurs a limit in the improvement of high frequency operation.
Second, after polycrystalline silicon which becomes the gate electrode 5 is embedded in the trench 23 by CVD, in order to remove other polycrystalline silicon on the surface of the semiconductor substrate except for the polycrystalline silicon in the trench, etch-back of the polycrystalline silicon is carried out. However, if the amount of etch-back is excessively large, the polycrystalline silicon in the trench is slightly etched, and an overlap portion between the polycrystalline silicon region which becomes the gate electrode 5 and the N-type high concentration region 21 disappears, so that a threshold voltage is greatly increased, or in the worst case, the transistor operation is lost.
The etching end time of this polycrystalline silicon is determined by detecting a difference in light emission in plasma when the under layer is exposed as a result of etching of the polycrystalline silicon on the surface of the substrate or by detecting a radical amount in an etching gas, and by adjusting an over etching amount from that. With respect to the etching amount of the polycrystalline silicon at this time, by using the foregoing detecting method, as compared with the silicon etching for forming the trench 23, although the fluctuation among wafers and lots can be lessened, wafer in-plane fluctuation can not be suppressed. Then, considering that the N-type high concentration source region 21 overlaps with the polycrystalline silicon which becomes the gate electrode 5 to perform the transistor operation even at a place where the etching amount is largest on the wafer surface, the over etching amount of the polycrystalline silicon is determined. Thus, on the wafer surface, there occurs fluctuation in the amount of the overlap between the N-type high concentration source region 21 and the polycrystalline silicon which becomes the gate electrode 5. A sample in which the overlap amount between the gate and source is large has a large capacitance between the gate and source, so that a trouble is still caused in the high frequency operation.
Third, since the P-type diffusion region 20 which becomes the body region is formed by ion implantation from the principal surface of the N-type epitaxial layer 2 and by the high temperature heat treatment, there is obtained such an impurity profile that the side of the N-type high concentration region 21 has the highest concentration, and the concentration of a portion becomes low as the portion approaches the drain. However, due to the diffusion fluctuation of the N-type high concentration region 21 and the implantation depth fluctuation of the P-type diffusion region 20, the peak concentration here is apt to fluctuate, and the threshold voltage is apt to fluctuate by this.
In order to solve the above problems, according to a first aspect of the present invention, a vertical MOS transistor includes a semiconductor substrate including a high concentration layer of a first conductivity type and an epitaxial layer on the high concentration layer, the epitaxial layer having the first conductivity type and a concentration lower than that of the high concentration layer; a recess portion formed from a principal surface of the semiconductor substrate toward the high concentration layer of the first conductivity type to have such a depth that it does not reach the high concentration layer of the first conductivity type; an insulating film covering a side face and a bottom face of the inside of the recess portion; a gate electrode made of polycrystalline silicon which is in contact with the insulating film and is embedded in the recess portion; a source region of the first conductivity type formed outside of the recess portion to be in contact with the recess portion and on the surface of the semiconductor substrate; a body region of a second conductivity type which is formed to be in contact with the recess portion and to surround the high concentration source region and is formed to a same depth as a bottom portion of the recess portion; and a drain electrode connected to the high concentration region of the first conductivity type of a rear face of the semiconductor substrate.
Besides, the vertical MOS transistor is characterized in that in the body region, an impurity concentration distribution in a depth direction from the source region to the epitaxial layer of the first conductivity type is constant.
Besides, the vertical MOS transistor is characterized in that a planar width of a region of the body region which is in contact with the recess portion and extends from the source region to the epitaxial layer of the first conductivity type is 0.5 xcexcm or less.
Besides, the vertical MOS transistor includes a gate electrode made of polycrystalline silicon being in contact with the insulating film and embedded to a halfway depth in the recess; a high concentration source region of the first conductivity type which is formed outside of the recess portion and is formed on the principal surface of the semiconductor substrate to be in contact with the recess portion and not to have an overlap portion with the polycrystalline silicon through the insulating film; and a low concentration source region of the first conductivity type which is formed to be in contact with the recess portion, is formed from a bottom of the high concentration source region to an upper end of the polycrystalline silicon, and has a concentration lower than the high concentration source region.
According to another aspect of the present invention, a vertical MOS transistor includes a semiconductor substrate including a high concentration layer of a first conductivity type and an epitaxial layer on the high concentration layer, the epitaxial layer having the first conductivity type and a concentration lower than that of the high concentration layer; a recess portion formed from a principal surface of the semiconductor substrate toward the high concentration layer of the first conductivity type to have such a depth that it does not reach the high concentration layer of the first conductivity type; an insulating film covering a side face and a bottom face of the inside of the recess portion; a gate electrode made of polycrystalline silicon which is in contact with the insulating film and is embedded to a halfway depth in the recess portion; a high concentration source region of the first conductivity type which is formed outside of the recess portion and is formed on the principal surface of the semiconductor substrate to be in contact with the recess portion and not to have an overlap portion with the polycrystalline silicon through the insulating film; a low concentration source region of the first conductivity type which is formed to be in contact with the recess portion, is formed from a bottom of the high concentration source region to an upper end of the polycrystalline silicon, and has a concentration lower than the high concentration source region; a body region of a second conductivity type which is formed to be in contact with the recess portion and to surround the high concentration source region and the low concentration source region; and a drain electrode connected to the high concentration region of the first conductivity type of a rear face of the semiconductor substrate.
Besides, the vertical MOS transistor is characterized in that the polycrystalline silicon in the recess portion is embedded to a depth of 0.5 to 0.8 xcexcm from the principal surface of the semiconductor substrate.
Besides, the vertical MOS transistor is characterized in that an overlap between the low concentration source region of the first conductivity type and the polycrystalline silicon through the insulating film in a depth direction is 0.1 xcexcm or less.
Besides, the vertical MOS transistor is characterized in that the concentration of the low concentration region of the first conductivity type is from 55xc3x971017/cm3 to 4xc3x971018/cm3, and the concentration of the body region of the second conductivity type is 2xc3x971016/cm3 to 5xc3x971017/cm3.
According to still another aspect of the present invention, a method of manufacturing a vertical MOS transistor includes the steps of forming an oxide film on a principal surface of a semiconductor substrate of a first conductivity type; depositing polycrystalline silicon on the oxide film; exposing the principal surface of the semiconductor substrate by patterning the polycrystalline silicon and the oxide film; forming a trench by etching the exposed semiconductor substrate together with the polycrystalline silicon by an anisotropic dry etching method; forming a gate insulating film on the inside of the trench; forming a body region of a second conductivity type by an ion implantation method at an irradiation angle varied according to a trench depth and a trench width; embedding polycrystalline silicon in the trench; forming a gate electrode in the trench by carrying out etch-back of the polycrystalline silicon; forming a low concentration source region of the first conductivity type by an ion implantation method at an inclined irradiation angle of 30xc2x0 or more with respect to a vertical direction; and forming a high concentration source region of the first conductivity type by an ion implantation method at an inclined irradiation angle of 7xc2x0 or less with respect to the vertical direction.
Besides, the method of manufacturing the vertical MOS transistor is characterized in that a laminate film forming planar patterning of the trench is an oxide film and a silicon nitride film in sequence from the principal surface of the semiconductor substrate.
Besides, the method of manufacturing the vertical MOS transistor is characterized in that a laminate film forming planar patterning of the trench is an oxide film and a photoresist in sequence from the principal surface of the semiconductor substrate.
Besides, the method of manufacturing the vertical MOS transistor is characterized in that an etching apparatus for forming the trench is made a same apparatus as an etching apparatus for carrying out etch-back of the polycrystalline silicon to form the gate electrode.